1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a MOS dynamic memory comprising a stacked memory capacitor.
2. Description of the Prior Art
To ensure cell capacity with high integration of an LSI memory, there has been developed and put to practical use a stacked memory capacitor in which the surface level difference among the lower layers of a semiconductor device is utilized on a three-dimensional basis.
FIG. 22 shows the layout of the stacked capacitor in the folded bit line form. In FIG. 22, the stacked capacitor has a plurality of cells 56 to 61 arranged in a direction of an arrows C and D. Each cell has a contact 53 for a node electrode and a node electrode 54, and a bit line contact region 55a, 55b, 55c, 55d or 55e and an active region 51 by half at the least on a semiconductor substrate. The semiconductor substrate has the active regions 51 and word lines (transfer gates) 52. The word lines 52 are extended in a direction (a direction of an arrow D) perpendicular to a longitudinal direction of the active regions 51 (the C direction).
The adjacent bit line contact regions 55a and 55b are arranged on the same line parallel with the D direction between the cells 56 and 57. In addition, the adjacent bit line contact regions 55c and 55d are arranged on the same line parallel with the D direction between the cells 58 and 59.
Furthermore, the projected shape of the node electrode 54 is a quadrangle which is adapted as a node electrode.
Each cell has a size S.sub.2 of 6 .mu.m in the C direction, and a size S.sub.4 of 2 .mu.m in the D direction.
As shown in FIGS. 23 and 24, the bit line contact region 55 includes a bit line contact hole 55d. The bit line contact hole 55d is formed between LOCOS films 70, 70 on a Si substrate 74 having the LOCOS films 70, SiO.sub.2 films 71, capacitor insulating films 72 and a plate electrodes 73. The contact hole 53 for the node electrode is formed between the transfer gate 52 which is provided on the LOCOS film 70 and the transfer gate 52 which is provided through a gate oxide film 81 on the Si substrate 74 having impurity diffusion layers 80, 80. The contact hole 53 is buried by a capacitor 84 comprised of the node electrode 54, the capacitor insulating film 72 and the plate electrode 73.
Referring to the memory in the folded bit line form, a short side m of the node electrode 54 is always set to the minimum dimension between the node electrodes 54, 54 which is defined by design rules. For this reason, the maximum projected area of the node electrode 54 is automatically determined by overlapping with each layer.
Referring to the cell layout mentioned above, however, the projected area of the node electrode is determined by overlapping with each layer. Consequently, when the cell size is specified, the cell capacity is determined.
Accordingly, the cell size is reduced with the high integration of the LSI memory. Consequently, it becomes more difficult to ensure the cell capacity.